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- Within the last 7 days 2,087
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(FMG016) | Senior IC Digital Design Engineer
StarIC Québec, QC
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
2 days ago in KitjobReport -
B964 Senior IC Digital Design Engineer
new StarIC Peterborough, ON
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
Senior IC Digital Design Engineer | LDR-677
StarIC Coquitlam, BC
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
2 days ago in KitjobReport -
Senior IC Digital Design Engineer (B35)
new StarIC St-Bruno-de-Montarville, QC +5 locations
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
[I430] - Senior IC Digital Design Engineer
new StarIC Toronto, ON +7 locations
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
EKD068 Senior IC Digital Design Engineer
StarIC Mirabel, QC
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
2 days ago in KitjobReport -
Senior IC Digital Design Engineer | (FFE-850)
new StarIC La Pocatiere, QC
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
FVX-192 - Senior IC Digital Design Engineer
StarIC Rouyn-Noranda, QC
...(academic work will be considered). Experience in VHDL and/or Verilog design and simulation. Front-End tools experience (Synopsys, Cadence and/or Mentor’s...
2 days ago in KitjobReport -
Senior IC Digital Design Engineer - (D967)
new StarIC Victoria, BC +7 locations
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
Senior IC Digital Design Engineer - VJB-610
new StarIC Lethbridge, AB
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
E-671 Senior IC Digital Design Engineer
new StarIC Saint Valere, QC
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
(XGH-804) Senior IC Digital Design Engineer
new StarIC La Pocatiere, QC
...(academic work will be considered). Experience in VHDL and/or Verilog design and simulation. Front-End tools experience (Synopsys, Cadence and/or Mentor’s...
1 day ago in KitjobReport -
(YH-152) Senior IC Digital Design Engineer
StarIC Québec, QC
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
2 days ago in KitjobReport -
(NCK-940) - Senior IC Digital Design Engineer
new StarIC Guelph, ON
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
(MKB-538) - Senior IC Digital Design Engineer
StarIC Val-d'Or, QC
...(academic work will be considered). Experience in VHDL and/or Verilog design and simulation. Front-End tools experience (Synopsys, Cadence and/or Mentor’s...
2 days ago in KitjobReport -
[GC-786] Senior IC Digital Design Engineer
StarIC Québec, QC
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
2 days ago in KitjobReport -
VSC475 Senior IC Digital Design Engineer
new StarIC Dartmouth, NS +1 Location
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
Senior IC Digital Design Engineer ZSL693
new StarIC Kingston, ON +2 locations
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
Senior IC Digital Design Engineer - [KJX244]
new StarIC London, ON
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
LTN776 - Senior IC Digital Design Engineer
new StarIC Halifax, NS +5 locations
...(academic work will be considered). Experience in VHDL and/or Verilog design and simulation. Front-End tools experience (Synopsys, Cadence and/or Mentor’s...
1 day ago in KitjobReport -
(JT235) - Senior IC Digital Design Engineer
new StarIC Gatineau, QC
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
Senior IC Digital Design Engineer [PYY-10]
new StarIC Joliette, QC
...(academic work will be considered). Experience in VHDL and/or Verilog design and simulation. Front-End tools experience (Synopsys, Cadence and/or Mentor’s...
1 day ago in KitjobReport -
(AI458) Senior IC Digital Design Engineer
new StarIC Granby, QC +1 Location
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
F669 Senior IC Digital Design Engineer
new StarIC Cambridge, ON +1 Location
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport -
Senior IC Digital Design Engineer - [RLA181]
new StarIC La Baie, QC
...(academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End tools experience (Synopsys, Cadence and/or Mentor’s)...
1 day ago in KitjobReport
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