Maintenance engineering job offers in qc

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  • Lead DevOps Engineer

    Playwire Saint-Nazaire-d`Acton, QC  +12 locations

    As a Lead DevOps Engineer, you will build out and maintain best-in-class DevOps and GitOps practices across the engineering group. In this role you will work...
    4 days ago in Jobrapido

    Report

  • Senior IC Digital Design Engineer

    new StarIC Saguenay, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    10 h 3 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Saint Valere, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    10 h 6 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC St-Bruno-de-Montarville, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    10 h 7 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Saint-Joseph-de-Beauce, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    10 h 8 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Val-d'Or, QC  +101 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    1 day ago in whatjobs

    Report

  • Lead DevOps Engineer

    Playwire Saint-Prosper-de-Dorchester, QC  +12 locations

    As a Lead DevOps Engineer, you will build out and maintain best-in-class DevOps and GitOps practices across the engineering group. In this role you will work...
    4 days ago in Jobrapido

    Report

  • Senior IC Digital Design Engineer

    new StarIC Québec, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    10 h 11 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Chambord, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    10 h 12 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Gatineau, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    16 h 45 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Joliette, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    16 h 48 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Victoriaville, QC  +101 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    1 day ago in whatjobs

    Report

  • Lead DevOps Engineer

    Playwire Chambord, QC  +12 locations

    As a Lead DevOps Engineer, you will build out and maintain best-in-class DevOps and GitOps practices across the engineering group. In this role you will work...
    4 days ago in Jobrapido

    Report

  • Senior IC Digital Design Engineer

    new StarIC Beloeil, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    16 h 50 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC La Pocatiere, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    16 h 54 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Sept-Îles, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    16 h 55 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Disraeli, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    16 h 56 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Rivière-du-Loup, QC  +101 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    1 day ago in whatjobs

    Report

  • Lead DevOps Engineer

    Playwire La Baie, QC  +12 locations

    As a Lead DevOps Engineer, you will build out and maintain best-in-class DevOps and GitOps practices across the engineering group. In this role you will work...
    4 days ago in Jobrapido

    Report

  • Senior IC Digital Design Engineer

    new StarIC Victoriaville, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    23 h 49 minutes ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Saint-Laurent, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    1 day ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Saint-Hyacinthe, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    1 day ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Becancour, QC  +69 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    1 day ago in Talent.com

    Report

  • Senior IC Digital Design Engineer

    new StarIC Terrebonne, QC  +101 locations

    ...Engineering 3 – 6 years of digital IC design experience (academic work will be considered) Experience in VHDL and/or Verilog design and simulation Front-End...
    1 day ago in whatjobs

    Report

  • Lead DevOps Engineer

    Playwire Saint Esprit, QC  +12 locations

    As a Lead DevOps Engineer, you will build out and maintain best-in-class DevOps and GitOps practices across the engineering group. In this role you will work...
    4 days ago in Jobrapido

    Report

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Maintenance engineering job offers in qc

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